International Symposium on Physical Design, April 2000, pp. International Conference on Computer Aided Design, November 2003, pp. Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting Tim Cheng, Elsevier Inc. International Conference on Computer-Aided Design, November 2000, pp. It presents test techniques with highly complex nanometer designs. In this talk, I will give a brief introduction to SoC testing of digital circuits.
International Symposium on Low Power Electronics and Design, August 2001, pp. The test synthesis flow typically includes testability rule checking and repair in the beginning to guarantee that the design has complied with all given testability rules. However, previous work on designing on-chip at-speed test clock controllers for multi-clock has quadratic increasing area overhead along with linearly increasing clocks. International Conference on Computer Design, September 2000, pp. Those circuits that fail to produce a correct response at any point during the test sequence are assumed to be faulty.
This technique is applicable to any combinational network in which none of the outputs depends on all inputs. These techniques are required to improve the product quality and reduce the defect level and test cost of a digital circuit, while at the same time simplifying the test, debug, and diagnosis tasks. Any single-event upsets can increase logic and memory soft error rates. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. Depending on needs, both input test stimuli and output response analysis can be generated and performed inside the chip.
These test techniques are developed for reliability screen or defective parts per million reductions. Scan is not sufficient because small feature size causes physical failures that are difficult to detect. Cheng-Kok Koh's Publications Research Publications The documents contained in this directory have been made available as a courtesy. Advances in semiconductor manufacturing technology have allowed the integration of a billion transistors in a nanometer design. International Conference on Computer-Aided Design, November 2000, pp.
Modern electronics testing has a legacy of more than 40 years. International Conference on Computer-Aided Design, November 2000, pp. Test techniques that have been practiced in industry to improve product quality and test cost are first described. Finally, a number of test compression circuit structures for test stimuli compression and test response compaction are presented. Circuits that produce the correct output responses for all input stimuli pass the test and are considered to be fault free. Yildiz, Satoshi Ono, Cheng-Kok Koh, and Patrick H. Design, Automation and Test in Europe Conference, March 2002, pp.
Test compression architectures designed to reduce test data volume and test application time are discussed. This chapter presents several promising techniques for testing nanometer designs that can cope with physical failures caused by signal integrity, defects, and process variations during manufacturing. The chapter also investigates that whether a design is implemented in a test-friendly manner and to recommend changes in order to improve the testability of the design for achieving the goals. International Symposium on Quality Electronic Design, March 2002, pp. International Conference on Computer Aided Design, November 2003, pp. International Symposium on Low Power Electronics and Design, August 2003, pp. Therefore, it is imperative to seek viable test solutions.
It is thus becoming crucial to ensure that the chips can still function at the end system in the presence of these defects and soft errors, especially when the chips are to be installed into airplanes, pacemakers, or cars for safety-critical concerns. Copyright and all rights therein are maintained by the authors or by other copyright holders. . All detectable, combinational faults those that do not change a combinational circuit to a sequential circuit in each cone of logic driving a single output are guaranteed to be detected. International Symposium on Quality Electronic Design, March 2002, pp. To test timing-related faults between synchronous clocks, an at-speed test clock and an automatic test pattern generation scheme are needed.
Kahng, Cheng-Kok Koh, and C. In both the cases, only a small number of scan chains are activated in a single cycle. The digital logic can be reconfigured in test mode to include test logic to improve the testability and test quality of the circuit. International Conference on Computer-Aided Design, November 2000, pp. The important and essential process of physical design automation is discussed as well.
To achieve high fault coverage, the proposed method uses pseudorandom patterns from a cellular automaton to locate defective chips, and walking sequences to locate bad interconnects. This chapter also covers a number of error-resilient and defect-tolerant designs embedded on-chip to tolerate soft errors and defects. The overhead is very low and the test time is short. It also identifies scan design rule violations and understands the basics for successfully converting a design into a scan design. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. International Conference on Computer Design, September 2000, pp. A few include on-chip hardware for stressing or special reliability measurements.